1. Field of the Invention
The present invention relates generally to a method of ion implantation, and more particularly to an ion implantation method carrying out a single step of ion implantation to produce impurity regions that vary in impurity concentration both in depth into and laterally on the surface of a wafer.
2. Description of the Background Art
Semiconductor devices have been developed remarkably in recent years. A fast operation and miniaturization of the devices are required as well as a good yield of production.
In order to achieve the miniaturization of the devices, an impurity diffusion layer is formed in a wafer of a semiconductor device. There are two methods as a method of forming the impurity diffusion layer: a method of implanting ions into the wafer, and a method of making ions permeate into the wafer. According to the ion implantation method, accelerated ions are implanted through a mask for ion implantation in depth into the surface of the wafer, go through the wafer and stop therein. Thereafter, the implanted ions are activated by heat treatment (annealing). Meanwhile, according to the ion permeation method, the wafer is placed in gas atmosphere at a high temperature including ions, and permeation of ions into the wafer and heat treatment (annealing) of the ions permeated are carried out at the same time; however, the ions permeate both laterally and longitudinally into the wafer, and thus it is difficult to accurately control the permeation of the ions.
Therefore, the ion implantation method is especially superior as a method of forming an impurity diffusion region in the wafer for achieving the miniaturization of the semiconductor device in the following characteristics: (1) The amount of and distribution of impurities in depth can be controlled accurately in accordance with acceleration voltage of ions, ion current and ion implantation time, and thus the same amount of and the same distribution of impurities in depth can be attained repetitively under the same control condition, (2) Impurities can be added uniformly over the whole surface of the wafer, (3) Selective implantations into micro portions are available or the like.
In order to optimally control an impurity profile (the profile here means distribution) formed in the inner portion of the wafer by employing the above ion implantation method, various methods have been developed of forming a mask for ion implantation.
FIGS. 9A-9G are sectional views showing one example of conventional steps of manufacturing a mask for ion implantation and forming a base region of a bipolar transistor and a conventional method of ion implantation, disclosed in Japanese Patent Publication No. 54-22275.
Referring to FIG. 9A, a SiO.sub.2 film 41 is formed on the surface of an n type Si substrate 40 with about 20.OMEGA.-cm of n type resistivity. The SiO.sub.2 film 41 is formed to a thickness of about 0.7 .mu.m by oxidation of the n type Si substrate 40 in wet oxygen at 1,200.degree. C. for about 50 min. The n type Si substrate 40 that the SiO.sub.2 film 41 is formed on its surface is then heated in a P.sub.2 O.sub.5 gas atmosphere at 1,100.degree. C. for about 30 min. to form a phospho-silicate glass layer 42 on the surface of the SiO.sub.2 film 41.
Referring to FIG. 9B, a SiO.sub.2 film 43 including P, which is a first shielding film, is formed on the surface of the n type Si substrate 40. The SiO.sub.2 film 43 is formed by heating the n type Si substrate 40 including the SiO.sub.2 film 41 and the phospho-silicate glass layer 42, shown in FIG. 9A, in a N.sub.2 gas atmosphere at 1,200.degree. C. for about two hours. In this case, the concentration of P included in the SiO.sub.2 film 43 is highest at its surface and becomes lower as a function of depth into the substrate.
As shown in FIG. 9C, a first ion implantation window 44 is then formed on the SiO.sub.2 film 43 by photo-etching. As more P becomes included in the SiO.sub.2 film 43, the etching rate of the SiO.sub.2 film 43 increases. Because the concentration of P is reduced as a function of depth into the substrate, the etching rate of the SiO.sub.2 film 43 decreases as a function of depth. Thus, an angle .theta. between the surface of the n type Si substrate 40 and the side surface of the ion implantation window 45 is approximately 170.degree., and thus the first ion implantation window 44 with a large side edge is formed.
In this case, an intersection 46 indicates an intersection between the side surface region of the ion implantation window 45 and the n type Si substrate 40, and an intersection 47 indicates an intersection between the surface of the SiO.sub.2 film 43 and the side surface region of the ion implantation window 45.
Next, as shown in FIG. 9D, an Al film 48 is formed by evaporation of Al on the surface of the SiO.sub.2 film 43 including P, without eroding the film 43. The Al film 48 is etchable, which is a second shielding film with a thickness of approximately 0.4 .mu.m.
As shown in FIG. 9E, a second ion implantation window 49 is formed on the Al film 48 by photo-etching. This ion implantation window 49 is formed about 10 .mu.m outward from the intersection 47 on the side surface of the first ion implantation window 45. B ions are then implanted in the n type Si substrate 40 under the condition of about 200 keV, about 1.times.10.sup.14 atoms/cm.sup.2. After ion implantation, a p.sup.+ region 50 is formed under a region of the first ion implantation window 44 where the SiO.sub.2 film 43 including P is etched away. The p.sup.+ region 50 is about 0.8 .mu.m deep at its deepest portion and is implanted with B ions of about 1.times.10.sup.14 atoms/cm.sup.2. Since the thickness of the SiO.sub.2 film 43 becomes greater from the intersections 46 to 47 on the side surface of the ion implantation window 45, an ion shielding effect becomes greater in B-ion implantation. Therefore, the depth of the p.sup.+ region 50 formed through B-ion implantation becomes smaller from the intersection 46 to the intersection 47, and thus the amount of B ions implanted in the n type Si substrate 40 is decreased. Furthermore, a small region 51 having a slightly reduced concentration of p type is formed in the n type Si substrate 40 beneath the SiO.sub.2 film 43 with a thickness of about 0.7 .mu.m. Moreover, since the Al film 48 of about 0.4 .mu.m in thickness is formed outside the second ion implantation window 49, no B-ions are implanted in the n type Si substrate 40 directly beneath the Al film 48.
Referring to FIG. 9F, the n type Si substrate 40 that the Al film 48 and SiO.sub.2 film 43 are removed is oxidized in dry oxygen at 1,000.degree. C. for about 90 min. This oxidization causes the depth of ion diffusion in the n type Si substrate 40 to be greater with a larger amount of B ions implanted. Thus, ions are diffused in the greatest depth at the central portion of the p.sup.+ region 50, thereby forming a deepest p.sup.+ impurity diffusion region 52. A p type diffusion region 53 is formed in a peripheral region of the central portion of the p.sup.+ region 50. The p type diffusion region 53 has a smaller depth of diffusion outward the p.sup.+ diffusion region 52 depending on the amount of ions to be implanted. Since the p region 51 is implanted with a smaller amount of B ions, the region 51 combines with n type impurities of the n type Si substrate 40 through oxidation, resulting in an n type high resistivity region 54. Further, a SiO.sub.2 film 55 is formed on the surface of the n type Si substrate 40.
Referring to FIG. 9G, a window for a contact is formed in the SiO.sub.2 film 55 with a portion of the SiO.sub.2 film 55 removed. An Al electrode 56 is formed in this window.
As described above, dual mask formations control the state of impurity profiles due to implantation of ions into the n type Si substrate 40.
However, in a first conventional example (referred to Japanese Patent Publication No. 54-22275), the SiO.sub.2 film and the Al film 48, which serve respectively as the first and second shielding films on the substrate 40 in ion implantation, are formed by photo-etching. Since the photo-etching requires a photo-mask alignment, there is a problem that as a design pattern on the substrate 40 is miniaturized, an influence due to accuracy of the photo-mask alignment becomes greater. Moreover, there are other problems as follows. In the formation of the ion implantation windows 44 and 49 by photo-etching, it is difficult to form the miniaturized pattern because of a poor control of the dimension of the windows in a horizontal direction. Further, in this example, it is possible to form an impurity profile with different depths successively in the wafer; however, it depends on its shape in etching a material to be a shielding film in impurity implantation, and hence, this profile has a limited shape and requires the dual mask alignment in formation of one impurity profile. Further, the formation of the impurity profile is time-consuming since it employs an etching technology. Thus, with the shape of the impurity profile in the wafer complicated, a plurality of the steps of forming the impurity profile are required, resulting in degradation in accuracy of the impurity profile.
FIGS. 10A-10H are sectional views showing another example of the conventional steps of manufacturing a mask for ion implantation and a conventional method of ion implantation using anisotropical etching, disclosed in Japanese Patent Laying Open No. 62-58682.
Referring to FIG. 10A, a p.sup.- Si substrate 61 is of high resistivity, and an isolation oxide film 62, e.g., a SiO.sub.2 film, is formed by selective oxidation process (or isoplanar). A gate oxide film 63 is a thin film of 500 to 1,000 .ANG. in thickness, formed on the surface of the p.sup.- Si substrate 61 by thermal oxidation. Further, a polysilicon gate 64 is made by patterning polysilicon, deposited on the gate oxide film 63 to a thickness of about 3,000 .ANG., so as to be of a predetermined gate length through photo-etching.
Ion-implanting of P type impurities into the p.sup.- Si substrate 61 formed as described causes formation of a low concentration impurity layer through the gate oxide film 63 in the surface of the p.sup.- Si substrate 61. In this ion implantation, the polysilicon gate 64 and the isolation oxide film 62 serve as shielding films for ion implantation.
Next, referring to FIG. 10B, an insulator film 65 is formed on the surfaces of the isolation oxide film 62, the gate oxide film 63 and the polysilicon gate 64. The insulator film 65 is of silicon oxide formed by CVD (Chemical Vapor Deposition), e.g., a high-temperature low-pressure growth. The insulator film 65 is formed to a thickness of 2,000 to 3,000 .ANG..
As shown in FIG. 10C, the insulator film 65 is etched away from its surface by dry etching. The dry etching is carried out by ion implantation with a CHF.sub.3 gas. At this time, inclining a direction of implanting ions by an angle .theta., e.g, about 20.degree.-30.degree., with respect to the right angle to the substrate, as shown in the figure, allows the insulator film 65 to remain at a portion contacting the polysilicon gate 64 and thus causes spacers 66 to be formed asymmetrically on opposite sides of the polysilicon gate 64.
As means for altering the direction of implanting ions, as shown in FIG. 10D, inclining the p.sup.- Si substrate 61 by an angle .theta. with respect to a vertical direction from an upper electrode R1 to a lower electrode R2 enables a selection of an arbitrary angle of implanting ions with respect to the p.sup.- Si substrate 61.
Alternatively, as shown in FIG. 10E, relatively and horizontally shifting the respective positions of the upper electrode R1 and the lower electrode R2 allows alteration of the direction of implanting ions (the angle .theta.) into the p.sup.- Si substrate 61 between these electrodes.
Next, as shown in FIG. 10F, As (arsenic) ions are implanted in the whole surface of the p.sup.- Si substrate 61 in which the spacers 66 are formed. The ions are introduced with high concentration into the surface of the p.sup.- silicon substrate 61 through the gate oxide film 63 to form a high concentration impurity layer. At this time, the polysilicon gate 64 and the spacers 66 serve as shielding films in ion implantation.
As shown in FIG. 10G, an offset gate n.sup.- layer 68, which is a low concentration n.sup.- layer to be an offset portion, is formed on the surface of the p.sup.- Si substrate 61 beneath the spacers 66, and at the same time, a source/drain n.sup.+ layer 67, which is a high concentration n.sup.+ layer to be a source/drain, is formed in the other portions of the substrate 61 where the spacers 66 are not formed. The layers 67 and 68 are formed by diffusing impurities such as P or As in the p.sup.- Si substrate 61 through annealing (a heat treatment). In this case, as for the width of the offset gate n.sup.- layer 68, the left side portion (the source side) of the layer 68 is formed in smaller width than the right portion (the drain side) in proportion to the width of the spacers 66 which are formed asymmetrically.
Next, as shown in FIG. 10H, a source/drain Al electrode 70 is formed to perfect an n channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) of an LDD (Lightly Doped Drain) structure. The source/drain Al electrode 70 is formed by forming a CVD.SiO.sub.2 film 69 or the like, as an insulation film on the whole surface of the p.sup.- Si substrate 61 shown in FIG. 10G, then etching away a source/drain portion by contact photo-etching, and depositing evaporated Al on this portion by photo-etching.
In another conventional example (referred to Japanese Patent Laying Open No. 62-58682), the spacers 66 serving as a shielding film in ion implantation are formed by anisotropic etching. However, there are problems in this example as follows. The anisotropic etching needs to limit a direction of a transistor with respect to a semiconductor substrate, and thus it is limited in pattern designing. In addition, since a ratio of the width of the larger spacer 66 formed in contact with the polysilicon gate 64 to that of the smaller spacer 66 depends on an angle of oblique anisotropic etching, it is difficult to increase this ratio. Furthermore, in this example, the source/drain is formed in the wafer asymmetrically; however, this formation depends on the oblique anisotropic etching of the spacers 66, so that a direction of the gate with respect to the substrate is limited to one direction. Moreover, due to this limitation of the oblique etching, the substrate should be set obliquely to the direction of ion implantation between the upper and lower electrodes. Therefore, the following disadvantages also arise. That is, a distance between these two electrodes is limited; the substrate is fixed with difficulty; and the impurity profile cannot have configurations.